This invention relates to semiconductor devices and more specifically relates to a process for the low cost manufacture of a novel semiconductor device.
In prior art semiconductor devices, the housing area is frequently a large multiple of the area of the semiconductor die contained therein. Further, in many known semiconductor device, heat is taken out only from one side of the die, usually the bottom surface. In addition, the process for the manufacturing of prior art semiconductor devices is costly, specially when single device handling techniques are used.
In the presently known semiconductor die, particularly power MOSgated die, the top electrode (the source) is generally an aluminum contact containing about 1.0% silicon (hereafter an aluminum contact). The aluminum contact is used because it is well adapted to the wafer manufacturing process. However, it is difficult to form electrical connections to such aluminum contacts so a wire bond process is usually used in which a wire is ultrasonically bonded to the underlying aluminum contact. These wire-bond connections have a limited area and are thus a source of electrical resistance (RDSON) and of heat generation during operation. However, the bottom drain contact of a conventional MOSgated die is frequently a trimetal which is easily solderable or otherwise electrically connectable to a wide area contact surface without wire bonding as shown, for example, in U.S. Pat. No. 5,451,544. Thus, heat is primarily removed from the silicon die at the back contact surface, even though most heat is generated at the junction in the top surface and at the wire bonds. It would be desirable to remove heat from such a bottom drain in an improved manner.
It is known that solderable top contacts can be made to the top surface of a die, as shown in U.S. Pat. No. 5,047,833. However, the packages used for such solderable top contact structures have had very large “footprints” in comparison to the die area.
It would be desirable to produce a semiconductor device and a process for its manufacture which would occupy a smaller area on a circuit and would exhibit a lower RDSON than the known semiconductor devices.
It would be further desirable to produce such devices in a process which permits batch handling with reduced equipment on the production line and lower costs.
Devices are known in which the source side of a MOSgated device wafer is covered with a passivation layer, preferably a photosensitive liquid epoxy, or a silicon nitride layer, or the like. To form the passivation layer, the wafer is coated by spinning, screening, or otherwise depositing the liquid epoxy onto the wafer surface. The material is then dried and the coated wafer is exposed using standard photolithographic and masking techniques to form openings in the passivation layer to produce a plurality of spaced exposed surface areas of the underlying source metal and a similar opening to expose the underlying gate electrode of each die on the wafer. Thus, the passivation layer acts as a conventional passivation layer, but further acts as a plating resist (if required) and as a solder mask, designating and shaping the solder areas. The openings in the novel passivation layer can be made through to a conventional underlying solderable top metal such as a titanium/tungsten/nickel/silver metal. Alternatively, if the underlying metal is the more conventional aluminum metal the exposed aluminum can be plated with nickel and gold flash or other series of metals, resulting in a solderable surface, using the passivation as a plating resist. The tops of the plated metal segments are easily solderable, or otherwise contacted with low resistance, as compared to the high resistance connection of the usual wire bond to an aluminum electrode.
The source contact areas may have various geometries and can even constitute a single layer area region.
The wafer is then sawn or otherwise singulated into individual die. The individual die are then placed source-side down and a U-shaped, an L-shaped or a cup shaped, partially plated drain clip is connected to the solderable drain side of the die, using a conductive epoxy or solder, or the like to bond the drain clip to the bottom drain electrode of the die. The bottoms of the posts of the drain clip may be coplanar with the source-side surface (that is the tops of the contact projections) of the die, or the source-side surface may be offset inwardly with respect to the bottoms of the post to improve reliability. The outer surface of the die is then overmolded in a mold tray. A large number of die with such drain clips can be simultaneously molded in the mold tray.
The bonding material may be protected with a fillet of passivation material or by overmolding all, or a part of the assembly. The parts can be made in production by using a lead frame, a continuous strip, or by molding devices in a single block and singulating devices from that block.
After molding, the devices are tested and laser marked and are again sawn into individual devices.
Devices of this kind are shown in a copending application Ser. No. 09/819,774, filed Mar. 28, 2001 entitled CHIP SCALE SURFACE MOUNTED DEVICE AND PROCESS OF MANUFACTURE, the disclosure of which is incorporated herein by reference.